FIG. 1 schematically shows an example of a phase-locked loop 10. The PLL 10 may comprise a phase detector 11, a low-pass filter 14, a voltage-controlled oscillator (VCO) 16, and a frequency divider 18. The phase detector 11 may have a first input connected or connectable to a reference signal provider (not shown), e.g., a clock which provides the phase detector 11 with a reference signal CLK that has a reference frequency Fref. The phase detector 11 may have second input connected to an output of the frequency divider 18. The low-pass filter 14 may have an input connected to an output of the phase detector 11. The VCO 16 may have an input connected to an output of the low-pass filter 14. The frequency divider 18 may have an input connected to an output of the VCO 16. In the example, the PLL further comprises a control unit, e.g., a sigma delta modulator 20, connected to the frequency divider 18 for controlling the division ratio of the frequency divider 18.
In operation, the phase detector 11 may compare a frequency divider output signal DIV from the frequency divider 18 against the reference signal CLK to determine a phase shift of the output signal from the frequency divider 18 relative to the reference signal CLK. A phase detection signal from the phase detector 11, indicative of the phase shift, may be passed through the low-pass filter 14 to filter out high frequency components from the phase detection signal. The filtered phase detection signal may be fed to the VCO 16, thus determining the oscillation frequency of the VCO 16. The VCO output signal, with frequency Fv, may be fed to the frequency divider 18 to generate the frequency divider output signal DIV of frequency Fv/N, N being the frequency division ratio of the frequency divider 18. Thus, a negative feedback loop for keeping the VCO phase-locked to the reference signal CLK may be provided.
The frequency division ratio N may be varied to generate frequency ramps of the VCO 16, i.e., ramps of the VCO frequency Fv. Frequency ramps are commonly used in radar applications, for example. In the example, frequency ramps may be generated by means of the sigma delta modulator 20.
FIG. 2 schematically illustrates an example of an embodiment of the PLL 10 shown in FIG. 1. The phase detector 11 may, for instance, comprise an XOR gate 12, and it may in this case be referred to as the XOR phase detector 11. An XOR phase detector may sometimes be preferred over a classic combination of a phase-frequency detector and a charge pump, e.g., when the PLL including the low pass filter 14 is to be implemented on a single chip. Lack of a charge pump can result in a lower level of noise.
The reference signal provider may, for example, be a crystal oscillator (XCO) 11. The frequency divider 18 may comprise a series of one or more frequency dividers, e.g., including at least a programmable fractional divider. In the example, the frequency divider 18 comprises a first divider 24, a second divider 26, and a third divider 28, with division ratios of, e.g., 8, N, and 2, respectively. The division ratio N may be a fractional number in the range of, e.g., 92 to 106. The division ratio N may be programmable by means of the sigma delta modulator 20. The sigma delta modulator 20 may be connected to the second frequency divider 26 in a negative feedback loop. The PLL 10 may further comprise a ramp generator 22, e.g., a digital ramp generator, connected to the sigma delta modulator 20 so as to define the division ratio N of the second frequency divider 26, e.g., in a time-dependent manner.
FIG. 3 schematically illustrates an example of the phase detector 11 and operation thereof. In the example, the phase detector 11 is an XOR phase detector comprising an XOR gate 12 and a level shifter 13. The XOR gate 13 may have a first input, a second input, and an output. The output of the XOR gate 12 may be connected to the low-pass filter 14 via the level shifter 13. The XOR gate 12 may be arranged such that its output is low when its inputs are both low or both high, and high when one of its inputs is low and the other one is high. Accordingly, in the time interval indicated as delta Φ in the Figure, the XOR output may be high. When the two input signals are in phase, ΔΦ is 0. The output of an XOR frequency detector is schematically illustrated as a function of the phase shift ΔΦ in FIG. 4. It is noted that the XOR may be incapable of discriminating between a positive and a negative phase shift ΔΦ.